Ever since they introduced the Core 2 Duo, Intel has been on a role, and with their latest announcement there doesn’t seem to be a quick end in sight. Back in January, Intel announced its plans for the much anticipated leap to the 45-nanometer production process, in conjunction with details about how its planning to get there using high-K plus metal gate technology.

The step to 45-nanometers is a major leap forward for the industry. One that prior to now was deemed almost impossible. However, if Moore’s Law was to remain accurate, something was bound to occur that would propel the industry forward; that something was to be high-K plus metal gate technology.

High-K plus metal gate refers to the use of materials with a high dielectric constant (K), which, relative to silicon dioxide, allows for far better current leakage control while not sacrificing any of the associated capacitance. Prior to the implementation of high-K dielectrics, transistors couldn’t be packed tighter together than was done in the 65-nanometer process, because of instability caused by current leakage. The leaking currents from one transistor could influence the performance of its neighbor, thus in effect creating a useless chip.

In order to create a more efficient and faster chip, the capacitance of the individual transistors needs to be relatively high. A basic transistor consists of a capacitor oxide insulator wedged between a gate and a silicon substrate. So, according to physics, if the thickness of the insulator is decreased, the capacitance of the overall structure will increase. Unfortunately, the current silicon dioxide insulator layer material has reached its effective limit of scaling at about 1 nanometer in thickness. What the high-K dielectric allows Intel to do is replace the silicon insulator with one that is thicker, thus reducing leakage, while still maintaining the same capacitance.

High-K dielectrics are not a new concept for Intel, but their upcoming processor, codenamed “Penryn” would be the first to actually use the technology outside of a lab. The concept has been around for quite a while, and Intel’s research into the technology dates back to 2003. According to Intel Senior Fellow Mark Bohr, the innovation afforded by high-K dielectrics is akin to the introduction of polysilicon gate MOS transistors back in the 60’s.

Intel also announced that the new Penryn processors slated to use this technology will benefit from a transistor density count of 410 million for dual-core models and 820 million for quad-cores. Furthermore Intel expects a 30 percent reduction in transistor switching power, a tenfold reduction in gate oxide leakage, and a fivefold decrease in source drain – pretty impressive, especially considering that AMD is still trying to catch up with Intel’s current 65-nanometer chips.

I’ve always been an AMD fan myself, but I must admit Intel is well on their way to securing a place in my new machine…